Compiler Engineer - Machine Learning Compiler
Palo Alto, CA
- Pay
- Salary not listed in the saved posting
- Work setup
- Unconfirmed
- Employment
Full-time — employment source
Employment type Full-time
Read the full posting
What you’ll work on
Full postingJoin us in building the next generation of AI compilers.
Contribute across the full compiler stack, including operator lowering, graph/IR transformations, optimization passes, and backend code generation
Tools in this posting
- C
- PyTorch
- Python
- C++
Source — Tool mentions in context
About us Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications—whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
The following would be nice to have, but is not required - Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with contributions to MLIR or LLVM projects a plus - Experience with optimization methods (LP/MIP, CP, SAT/SMT) using solvers like Gurobi or OR-Tools for scheduling and resource allocation
- 3+ years of experience building compilers or high-performance systems software, especially those involving complex resource management or optimization. - Expert in modern C++ (C++14/17/20) and strong Python. - Experience with compiler IRs (SSA-based or graph-based), transformations, and code generation
About Mythic-Ai.com
Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost.
In the employer’s words · Read in context
Job description
Here's what you will do
- Contribute across the full compiler stack, including operator lowering, graph/IR transformations, optimization passes, and backend code generation
- Optimize for dataflow architectures, developing pipelined schedules, memory orchestration, and resource-constrained execution strategies
- Collaborate with hardware architects to influence architectural features, ensuring the compiler and hardware evolve together
- Develop compilation strategies that unify our analog compute with digital subsystems
- Build and maintain a compiler that produces high-performance binaries with strong debugging support, clear error messages, and predictable performance models
Here's the background we hope you will have
- 3+ years of experience building compilers or high-performance systems software, especially those involving complex resource management or optimization.
- Expert in modern C++ (C++14/17/20) and strong Python.
- Experience with compiler IRs (SSA-based or graph-based), transformations, and code generation
- Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures
The following would be nice to have, but is not required
- Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with contributions to MLIR or LLVM projects a plus
- Experience with optimization methods (LP/MIP, CP, SAT/SMT) using solvers like Gurobi or OR-Tools for scheduling and resource allocation
- Experience compiling for specialized accelerators (GPU, NPU, FPGA, or custom ASIC) on DNN workloads; GPU/DSP experience is valuable if combined with compiler backend work beyond kernel tuning
- Familiarity with heterogeneous compilation, especially mixing custom accelerators with CPUs/GPUs/NPUs, and exposure to analog or in-memory compute is a plus
- Experience collaborating in compiler–hardware co-design (architecture + ISA) for better compiler usability and hardware efficiency
What we offer
- The opportunity to shape how deep learning and LLM workloads are compiled on novel hardware.
- A role that spans software and hardware co-design, shaping both the compiler and the accelerator architecture
- A collaborative, innovative team that values engineering rigor, continuous integration, and user-focused design. We foster an environment of shared learning and technical excellence
- Competitive compensation, equity, and benefits package
Employment type
Full-time
Your next step
- Have your CV and examples of relevant work ready.
- Check the listed location, eligibility and core experience before starting.
- Ask the employer about the salary range before committing time to the process.
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Source & posting history
Source notes
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- Pay
No pay amount identified in the saved description.
- Location & working pattern
Palo Alto, CA
Working pattern and location restrictions need checking in the full posting.
- Work authorization
No clear work-authorization passage found. Eligibility is unconfirmed.
- Status in our records
- Active
- First seen by us
- Jun 2, 2026
- Recorded sightings
- 48
- Last seen by us
- Oct 12, 2026
- Employer says posted
- Oct 3, 2025
These dates show when we found the listing. Check the employer’s website to confirm it is still accepting applications.
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