3DIC Yield Analytics & Diagnostics Engineer, Staff
Hsinchu, Hsinchu City, TW
- Pay
- Pay not listed
- Work setting
- Not stated
- Employment
Full-time — employment source
Employment type in the employer’s posting: FULL_TIME
From the employer’s posting
What you’ll work on
Full postingAnalyze large-scale yield and diagnostics datasets to find systematic failure mechanisms
Run root-cause analysis by correlating electrical, process, design and assembly data
Perform advanced diagnostics on chiplets, stacked DRAM, TSVs, interposers and micro-bumps
Build yield analytics frameworks and dashboards for product and manufacturing visibility
Support new product introduction and high-volume manufacturing with yield risk monitoring
From the employer’s posting
Analyze large-scale yield and diagnostics datasets to identify systematic, random, and parametric failure mechanisms.
Drive structured root-cause analysis (RCA) and validate failure mechanisms through correlation of electrical, process, design, packaging, and assembly data.
Perform advanced diagnostics to isolate failure mechanisms across chiplets, logic die, stacked DRAM, TSVs, interposers, micro-bumps, hybrid bonding interfaces, and package substrates.
Develop analytics frameworks, dashboards, and yield-monitoring methodologies to improve product and manufacturing visibility.
Support New Product Introduction (NPI) and high-volume manufacturing (HVM) by identifying yield risks and establishing robust monitoring strategies.
What you’ll bring
All qualificationsCore experience
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Qualification wording
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Education & alternatives
Qualifications * Bachelor's degree in Engineering or related field with 6+ years of relevant experience, OR Master's degree with 5+ years, OR Ph.D. with 4+ years. * Strong experience in semiconductor yield analytics, diagnostics, and manufacturing data analysis.
Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Tools in this posting
- Python
- SQL
- Power BI
Source — Tool mentions in context
* Strong understanding of semiconductor test methodologies, failure analysis, and yield learning processes. * Proficiency with analytical tools such as Python, JMP, SQL, Yield Explorer, Power BI, or equivalent platforms. * Strong statistical analysis, problem-solving, and technical leadership skills.
Posting record
Report an error- Status in our records
- Live
- First seen by us
- Aug 15, 2026 · 76 days ago
- Recorded sightings
- 146
- Last seen by us
- Oct 30, 2026
- Employer says posted
- Jul 10, 2026
These dates show when we found the posting. Check the employer’s website to confirm it is still accepting applications.
Your next step
- Have your resume and examples of relevant work ready.
- Check the listed location, eligibility and core experience before starting.
- Ask the employer about the pay range before committing time to the process.
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Job description
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- Pay
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- Location & working pattern
Hsinchu, Hsinchu City, TW
* Develop and scale methodologies for analyzing heterogeneous data sources, including wafer sort, final test, package test, reliability, module-level, and stack-level data. * Perform advanced diagnostics to isolate failure mechanisms across chiplets, logic die, stacked DRAM, TSVs, interposers, micro-bumps, hybrid bonding interfaces, and package substrates. * Drive structured root-cause analysis (RCA) and validate failure mechanisms through correlation of electrical, process, design, packaging, and assembly data.
More source context
Preferred Qualifications * Deep understanding of 2.5D/3DIC architectures, chiplet integration, TSV/interposer technologies, hybrid bonding, and advanced packaging flows. * Experience building and scaling yield analytics frameworks, diagnostics methodologies, and data infrastructure.
- Work authorization
No clear work-authorization passage found. Eligibility is unconfirmed.
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