EDA AI/ML Layout Engineering Intern
Calabasas, California
- Pay
Multiple pay statements — pay source
CA Pay Range Master's: Min $40.32 to Max $43.42 PhD: Min $40.32 to Max $53.67
Master's: Min $40.32 to Max $43.42 PhD: Min $40.32 to Max $53.67 Relocation is available.
Read the full posting- Work setting
- Not stated
- Employment
- Not stated
Before you apply
- Eligibility
Visa Sponsorship is not available for this position. — eligibility source
Visa Sponsorship is not available for this position.
Read the full posting
What you’ll work on
Full postingDevelop AI and ML solutions for RFIC and analog layout automation
Assist in developing parameterized cells (PCells) and layout generation workflows
Research and prototype machine learning techniques for layout synthesis
Contribute to surrogate modeling and design space exploration frameworks
Build data generation, training, and evaluation pipelines for AI-driven EDA workflows
From the employer’s posting
Develop AI and ML solutions for RFIC and analog layout automation
Assist in the development of parameterized cells (PCells) and layout generation workflows
Research and prototype machine learning techniques for layout synthesis and design optimization
Contribute to surrogate modeling and design space exploration frameworks
Build data generation, training, and evaluation pipelines for AI-driven EDA workflows
What you’ll bring
All qualificationsCore experience
- Familiarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn
- Solid understanding of data structures, algorithms, and object-oriented programming
Preferred experience
- Familiarity with layout automation, PCell development, computational geometry, and design-rule-aware layout generation
- Familiarity with Git and modern software development practices
- Master's: Min $40.32 to Max $43.42
- Experience with C++, Rust, or performance-oriented software development
Qualification wording
Familiarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn
Solid understanding of data structures, algorithms, and object-oriented programming
Familiarity with layout automation, PCell development, computational geometry, and design-rule-aware layout generation
Familiarity with Git and modern software development practices
Master's: Min $40.32 to Max $43.42
Experience with C++, Rust, or performance-oriented software development
Education & alternatives
Minimum Qualifications - Currently pursuing a Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or a related technical field - Strong programming skills in Python
CA Pay Range Master's: Min $40.32 to Max $43.42 PhD: Min $40.32 to Max $53.67
Master's: Min $40.32 to Max $43.42 PhD: Min $40.32 to Max $53.67 Relocation is available.
Tools in this posting
- C++
- Python
- PyTorch
- scikit-learn
- TensorFlow
Source — Tool mentions in context
- Build data generation, training, and evaluation pipelines for AI-driven EDA workflows - Develop software components in Python and potentially C++ under mentorship - Evaluate AI-assisted design methodologies using real-world semiconductor design problems
- Exposure to surrogate modeling, Bayesian optimization, reinforcement learning, and design space exploration techniques - Experience with C++, Rust, or performance-oriented software development - Exposure to software development on Windows or Linux platforms
- Currently pursuing a Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or a related technical field - Strong programming skills in Python - Familiarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn
- Strong programming skills in Python - Familiarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn - Solid understanding of data structures, algorithms, and object-oriented programming
Posting record
Report an error- Status in our records
- Live
- First seen by us
- Oct 1, 2026 · 29 days ago
- Recorded sightings
- 150
- Last seen by us
- Oct 30, 2026
- Employer says posted
- Sep 29, 2026
These dates show when we found the posting. Check the employer’s website to confirm it is still accepting applications.
Your next step
- Have your resume and examples of relevant work ready.
- Check the listed location, eligibility and core experience before starting.
Complete your application on careers-keysight.icims.com. The employer’s form will show what is required.
Already applied? Track this application
Job description
Keysight is a mission-critical design enablement partner for organizations solving the world’s most complex engineering challenges. With deep engineering expertise and leading design, emulation, and test solutions, our ~16,800 employees help customers in over 100 countries accelerate innovation across communications, automotive, energy, quantum, aerospace and defense, semiconductor, and artificial intelligence markets. Learn more about what we do.
At Keysight, people come together to explore new ideas, challenge what's possible, and advance the technologies defining the future. Here, you'll find opportunities to do your best work, take your career further, and thrive in an award-winning culture. Learn more about our benefits.
Responsibilities
At Keysight EDA, we are developing next-generation AI-powered Electronic Design Automation (EDA) technologies to accelerate RFIC and analog IC design. As an EDA AI/ML Layout Engineering Intern, you will contribute to innovative solutions that apply machine learning, optimization, and software engineering to automate layout generation, PCell development, and design space exploration.
Working alongside EDA engineers, AI researchers, and RFIC domain experts, you will help develop intelligent workflows that improve designer productivity and accelerate chip development.
Key Responsibilities
- Develop AI and ML solutions for RFIC and analog layout automation
- Research and prototype machine learning techniques for layout synthesis and design optimization
- Assist in the development of parameterized cells (PCells) and layout generation workflows
- Work on geometric, topological, and rule-aware layout generation techniques
- Contribute to surrogate modeling and design space exploration frameworks
- Build data generation, training, and evaluation pipelines for AI-driven EDA workflows
- Develop software components in Python and potentially C++ under mentorship
- Evaluate AI-assisted design methodologies using real-world semiconductor design problems
- Collaborate with EDA engineers and RFIC designers to validate solutions
Qualifications
Minimum Qualifications
- Currently pursuing a Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or a related technical field
- Strong programming skills in Python
- Familiarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn
- Solid understanding of data structures, algorithms, and object-oriented programming
- Strong analytical and problem-solving skills
- Interest in AI/ML applied to engineering design automation
Preferred Qualifications
- Coursework or research in RFIC Design, Analog IC Design, VLSI Physical Design, EDA/CAD, or Semiconductor Design Automation
- Familiarity with layout automation, PCell development, computational geometry, and design-rule-aware layout generation
- Exposure to surrogate modeling, Bayesian optimization, reinforcement learning, and design space exploration techniques
- Experience with C++, Rust, or performance-oriented software development
- Exposure to software development on Windows or Linux platforms
- Familiarity with Git and modern software development practices
- Interest in AI-assisted schematic generation, layout synthesis, semiconductor design workflows, and next-generation AI-powered EDA tools
- Interest in learning about multithreaded applications and desktop software development
- Curiosity and eagerness to work in an Agile, collaborative team environment
CA Pay Range
Master's: Min $40.32 to Max $43.42
PhD: Min $40.32 to Max $53.67
Relocation is available.
Visa Sponsorship is not available for this position.
Please note, candidates must possess valid work authorization for the duration of the internship. International students requiring work authorization should work with their university to obtain and maintain appropriate CPT or other eligible employment authorization prior to the internship start date.
Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***
Source details
Source notes
Source excerptsSelected passages from the saved posting. Check the full description for conditions and exceptions.
- Pay
CA Pay Range Master's: Min $40.32 to Max $43.42 PhD: Min $40.32 to Max $53.67
More source context
Master's: Min $40.32 to Max $43.42 PhD: Min $40.32 to Max $53.67 Relocation is available.
- Location & working pattern
Calabasas, California
Working pattern and location restrictions need checking in the full posting.
- Work authorization
Relocation is available. Visa Sponsorship is not available for this position. Please note, candidates must possess valid work authorization for the duration of the internship. International students requiring work authorization should work with their university to obtain and maintain appropriate CPT or other eligible employment authorization prior to the internship start date. Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***
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