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Staff Defect Metrology AI/ML Engineer

Goleta, California, United States

Actively hiring, first seen by us today
Pay
$120,000–160,000/year — pay source
Additional Information The expected annual pay range for this position is $120,000 - $160,000. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate. Renesas offers a full range of elective benefits including medical, health savings account (with applicable medical plan), dental, vision, health and/or dependent care flexible spending accounts, pre-tax commuter benefits, life insurance, AD&D, and pet insurance. In addition to elective benefit options, benefited employees receive company-paid life insurance and AD&D, LTD, short term medical benefits as well as paid sick time, paid holidays, and accrued paid vacation. New employees will attend a detailed benefit orientation to learn more about our many benefits and resources.
Read the full posting
Work setting
On-site — work setting source
Work setup in the employer’s posting: On-site
From the employer’s posting
Employment
Full-time — employment source
Employment type in the employer’s posting: Full-time
From the employer’s posting

Before you apply

Work authorization
Must already have the right to work in the USApplicants for this position must be currently authorized to work in the United States on a full-time basis

What you’ll work on

Full posting
  • Develop image-processing algorithms and AI/ML models to detect, classify, and quantify semiconductor defects such as particles, pits, and scratches.

  • Analyze large datasets from wafer inspection, metrology, and MOCVD processes to identify trends, correlations, anomalies, and root causes.

  • Develop automated analysis and visualization workflows using Python, SQL, JMP, Excel, and related tools.

From the employer’s posting
Key Responsibilities: Develop image-processing algorithms and AI/ML models to detect, classify, and quantify semiconductor defects such as particles, pits, and scratches. Analyze large datasets from wafer inspection, metrology, and MOCVD processes to identify trends, correlations, anomalies, and root causes.
Develop image-processing algorithms and AI/ML models to detect, classify, and quantify semiconductor defects such as particles, pits, and scratches. Analyze large datasets from wafer inspection, metrology, and MOCVD processes to identify trends, correlations, anomalies, and root causes. Develop automated analysis and visualization workflows using Python, SQL, JMP, Excel, and related tools.
Analyze large datasets from wafer inspection, metrology, and MOCVD processes to identify trends, correlations, anomalies, and root causes. Develop automated analysis and visualization workflows using Python, SQL, JMP, Excel, and related tools. Correlate incoming substrate defects with epitaxial defects and develop data-driven methods for substrate quality screening.

What you’ll bring

All qualifications

Core experience

  • Experience in semiconductor defect inspection, metrology, yield engineering, manufacturing analytics, image analysis, or a related area.
  • Experience with AI/ML-based wafer defect detection or classification.
  • Experience applying AI/ML, computer vision, statistical learning, or advanced analytics to engineering problems.
  • Experience developing automated data pipelines, dashboards, or manufacturing analytics tools.
  • Experience working with large datasets, including data extraction, manipulation, statistical analysis, visualization, and correlation.
  • Experience with optical wafer inspection systems such as KLA Candela or Nanotronics.

Preferred experience

  • Familiarity with tools/libraries such as pandas, NumPy, scikit-learn, OpenCV, PyTorch, or TensorFlow is desirable.
Qualification wording
Experience in semiconductor defect inspection, metrology, yield engineering, manufacturing analytics, image analysis, or a related area.
Experience with AI/ML-based wafer defect detection or classification.
Experience applying AI/ML, computer vision, statistical learning, or advanced analytics to engineering problems.
Experience developing automated data pipelines, dashboards, or manufacturing analytics tools.
Experience working with large datasets, including data extraction, manipulation, statistical analysis, visualization, and correlation.
Experience with optical wafer inspection systems such as KLA Candela or Nanotronics.
Familiarity with tools/libraries such as pandas, NumPy, scikit-learn, OpenCV, PyTorch, or TensorFlow is desirable.
Education & alternatives
Required - BS with 5+ years, MS with 3+ years, or PhD in Engineering, Science, Data Science, Computer Science, or a related field. - Experience in semiconductor defect inspection, metrology, yield engineering, manufacturing analytics, image analysis, or a related area.
Apply at Renesas Electronics

Posting record

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Actively hiringFirst seen by us today, still listed, and not a repost of an earlier posting.

Status in our records
Live
First seen by us
Nov 6, 2026today
Recorded sightings
1

These dates show when we found the posting. Check the employer’s website to confirm it is still accepting applications.

How this job compares

Pay

Lower than most similar jobs

$120K–$160K against $166K–$240K, the middle half of what similar US postings state.

From 1,319 postings in the last year. Stated ranges, not salaries paid.

Time since we first saw it

Day 0

Early. Similar jobs usually come down between day 6 and day 71.

At Renesas Electronics, jobs usually come down by about day 37.

From 4,626 similar postings that came down, and 45 of Renesas Electronics’s. Coming down is not always a hire.

Renesas Electronics is hiring

6 open jobs

Open jobs by the week we first saw them, last 12 weeks.

  • Hiring has slowed
  • Takes jobs down at a usual pace
Hiring record

See how this role fits your experience

Add your resume and we’ll mark which of these tools you already use, and point out anything in the posting that could rule you out.

  • Python
  • SQL
  • Excel
  • NumPy
  • pandas
  • PyTorch
  • scikit-learn
  • TensorFlow
Where the posting names them
Job Description We are seeking a highly motivated Staff Engineer, Defect Metrology to join our MOCVD team. This role will provide technical leadership in semiconductor defect inspection, data analytics, and development of advanced defect detection and classification capabilities. The ideal candidate combines hands-on semiconductor metrology experience with strong skills in Python, data analysis, image processing, and AI/ML to improve product quality, process control, and manufacturing yield. Key Responsibilities:
- Analyze large datasets from wafer inspection, metrology, and MOCVD processes to identify trends, correlations, anomalies, and root causes. - Develop automated analysis and visualization workflows using Python, SQL, JMP, Excel, and related tools. - Correlate incoming substrate defects with epitaxial defects and develop data-driven methods for substrate quality screening.
- Experience in semiconductor defect inspection, metrology, yield engineering, manufacturing analytics, image analysis, or a related area. - Strong data analysis and programming skills, preferably with Python and SQL. - Experience applying AI/ML, computer vision, statistical learning, or advanced analytics to engineering problems.
- Experience working with large datasets, including data extraction, manipulation, statistical analysis, visualization, and correlation. - Familiarity with tools/libraries such as pandas, NumPy, scikit-learn, OpenCV, PyTorch, or TensorFlow is desirable. - Strong organizational skills, attention to detail, and demonstrated analytical and problem-solving capabilities.

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Demand for ML Engineer roles

New ML Engineer postings at the employers we follow are up 12% over the last 5 weeks compared with the 5 before.

Weekly new ML Engineer postings at the same employers, from the week of August 17 to the week of October 26. The fewest in a week was 624, the most 1,094, and the latest week had 870.
August 17Last week

Each bar is one week of new postings. The darkest bars are the last 5 weeks.

Counted from the hiring pages we’ve followed for at least five weeks, so employers we add don’t look like growth. Updated weekly.

About the role

We file this job under ML Engineer, by the work the posting describes.

ML engineers put machine learning models into products. They write the code that trains, ships, serves and monitors models so a recommendation or prediction works for real users.

Postings ask for strong Python and software engineering, a framework such as PyTorch, cloud services, and more and more often experience with large language models.

A data scientist often works out which model to build; an ML engineer makes it run reliably in production.

US government figures for computer and information research scientists

Median yearly pay, May 2025
$140,300
Expected change, 2025 to 2035
21.8% more jobsagainst 3.5% for all jobs

The government has no code for ML engineers, so these figures are for the closest group, computer and information research scientists.

Source: US Bureau of Labor Statistics, Occupational Employment and Wage Statistics (May 2025) and Employment Projections (2025 to 2035). Occupation code 15-1221.

Job description

View original posting ↗

Job Description

We are seeking a highly motivated Staff Engineer, Defect Metrology to join our MOCVD team. This role will provide technical leadership in semiconductor defect inspection, data analytics, and development of advanced defect detection and classification capabilities. The ideal candidate combines hands-on semiconductor metrology experience with strong skills in Python, data analysis, image processing, and AI/ML to improve product quality, process control, and manufacturing yield.

Key Responsibilities:

  • Develop image-processing algorithms and AI/ML models to detect, classify, and quantify semiconductor defects such as particles, pits, and scratches.
  • Analyze large datasets from wafer inspection, metrology, and MOCVD processes to identify trends, correlations, anomalies, and root causes.
  • Develop automated analysis and visualization workflows using Python, SQL, JMP, Excel, and related tools.
  • Correlate incoming substrate defects with epitaxial defects and develop data-driven methods for substrate quality screening.
  • Integrate defect, process, equipment, and wafer-level data to improve understanding of defect mechanisms and yield drivers.
  • Partner with process, equipment, and development engineers to correlate defect excursions with process changes and equipment events.
  • Improve inspection methodologies, algorithms, calibrations, statistical metrics, and defect classification strategies.
  • Ensure the accuracy, repeatability, and integrity of defect metrology systems and associated data.
  • Apply DOE, SPC, statistical modeling, and data visualization to support process improvement.
  • Communicate technical findings and actionable recommendations to engineering teams, management, vendors, and customers.

Qualifications

Required 

  • BS with 5+ years, MS with 3+ years, or PhD in Engineering, Science, Data Science, Computer Science, or a related field.
  • Experience in semiconductor defect inspection, metrology, yield engineering, manufacturing analytics, image analysis, or a related area.
  • Strong data analysis and programming skills, preferably with Python and SQL.
  • Experience applying AI/ML, computer vision, statistical learning, or advanced analytics to engineering problems.
  • Experience working with large datasets, including data extraction, manipulation, statistical analysis, visualization, and correlation.
  • Familiarity with tools/libraries such as pandas, NumPy, scikit-learn, OpenCV, PyTorch, or TensorFlow is desirable.
  • Strong organizational skills, attention to detail, and demonstrated analytical and problem-solving capabilities.
  • Strong teamwork and collaboration skills, with the ability to work effectively across process, equipment, manufacturing, development, and data/IT functions.

Preferred 

  • Experience with AI/ML-based wafer defect detection or classification.
  • Experience developing automated data pipelines, dashboards, or manufacturing analytics tools.
  • Experience with optical wafer inspection systems such as KLA Candela or Nanotronics.
  • Knowledge of semiconductor materials, epitaxial growth, and materials characterization.
  • Experience with DOE, SPC, process capability, and statistical modeling.
  • Familiarity with cleanroom protocols and semiconductor wafer handling.

Applicants for this position must be currently authorized to work in the United States on a full-time basis. Renesas is unable to sponsor applicants for work visas for this position

Additional Information

The expected annual pay range for this position is $120,000 - $160,000. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.

Renesas offers a full range of elective benefits including medical, health savings account (with applicable medical plan), dental, vision, health and/or dependent care flexible spending accounts, pre-tax commuter benefits, life insurance, AD&D, and pet insurance. In addition to elective benefit options, benefited employees receive company-paid life insurance and AD&D, LTD, short term medical benefits as well as paid sick time, paid holidays, and accrued paid vacation. New employees will attend a detailed benefit orientation to learn more about our many benefits and resources.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

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Pay
Additional Information The expected annual pay range for this position is $120,000 - $160,000. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate. Renesas offers a full range of elective benefits including medical, health savings account (with applicable medical plan), dental, vision, health and/or dependent care flexible spending accounts, pre-tax commuter benefits, life insurance, AD&D, and pet insurance. In addition to elective benefit options, benefited employees receive company-paid life insurance and AD&D, LTD, short term medical benefits as well as paid sick time, paid holidays, and accrued paid vacation. New employees will attend a detailed benefit orientation to learn more about our many benefits and resources.
Location & working pattern

Goleta, California, United States

Working pattern and location restrictions need checking in the full posting.

Work authorization
- Familiarity with cleanroom protocols and semiconductor wafer handling. Applicants for this position must be currently authorized to work in the United States on a full-time basis. Renesas is unable to sponsor applicants for work visas for this position Additional Information

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